MCIT/DIT-SMDP IEPs

Various IEPs conducted under DIT-SMDP were as follows :

Instruction Enhancement Programme Calendar
S. No. IEP Topic Co-ordinating RC Dates
1. VLSI Subsystem Design (B-4 + L-6) CEERI-Pilani December, 2000
2. Device Modeling (B-2 + L-7) IIT-Kanpur December, 2000
3. VLSI Fabrication Technology (B-1 + L-5) IIT-Kharagpur February, 2001
4. High-Level VLSI Design (B-7 + L-2 + L-3) CEERI-Pilani June, 2001
5. VLSI Design (B-3 + B-6 + L-1) IISc-Bangalore August, 2001
6. VLSI Testing (E-4) IIT-Kanpur October, 2001
7. VLSI Systems and Architectures (E-2) CEERI-Pilani December, 2001
8. Combinatorial Algorithms (B-8) IIT-Bombay February, 2002
9. VLSI Interconnects (E-8) IIT-Kharagpur February, 2002
10. FPGA and System Design (E-3 + E-5 + L-4) IIT-Bombay June, 2002
11. Analog and Mixed-Signal Design (B-5 + E-1 + L-8) IIT-Madras June, 2002
12. Hardware-Software Codesign (E-6) IIT-Delhi October, 2002
13. Low-Power Design (E-7) IISc-Bangalore December, 2002
14. Advanced System Design (E-10) IIT-Kharagpur December, 2002
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Contact Raj Singh for any suggestions or problems.

Updated : February 16, 2005
Created : September 17, 2000

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