Report of Activities Under the MoU

CEERI, Pilani and IIT, Delhi

August, 1994 -- June, 1997


A Memorandum of Understanding (MoU) was signed between IIT Delhi and CEERI, Pilani on 11th August, 1994. The scope of the MoU includes the following activities in specified areas of co-operation :
  1. Joint Sponsored Research and Consultancy Projects
  2. Exchange/Deputation of Staff
  3. Joint Conference/Workshop/Courses
  4. Sharing of Facilities
  5. Student-Level Interactions/Training
  6. Ph.D. Registration
Following is the summary of the activities carried out under the MoU from August, 1994 to June, 1997.

Academic Year 1994-95

Exchange/Deputation of Staff

Sharing of Facilities

Student-Level Training/Interaction


Academic Year 1995-96

Joint Sponsored Project

Exchange/Deputation of Staff

Sharing of Facilities

Student-Level Training/Interaction

Ph.D. Registration


Academic Year 1996-97

Exchange/Deputation of Staff

Joint Conferences/Workshops

Sharing of Facilities

Student-Level Training/Interaction


APPENDIX I

Areas of Co-operation for 1994-95

Microelectronics Area
  1. Fault Diagnosis and Fault Tolerant Design.
  2. Semiconductor Device Modeling and Reliability.
  3. Design and Fabrication of Test Chips.
  4. High Level Synthesis and Design of Microprocessor Architectures.
  5. Design of High Speed Logic Cells/Analog and Mixed A/D Circuits.
  6. Fuzzy Logic and Neural Networks.
  7. Thin Films.
Power Electronics Area
  1. ASIC and Gate-Array Implementation of Power Electronics Circuits.
  2. PWM Techniques and Their Applications.
  3. Position and Velocity Control Techniques in DC Drives.
Microprocessor Applications and Control Area
  1. Microprocessor Control of Process Industries.
  2. Microprocessor Applications.

Areas of Co-operation for 1995-96

Microelectronics Area
  1. Fault Diagnosis and Fault Tolerant Design.
  2. Semiconductor Device Modeling and Reliability.
  3. Design and Fabrication of Test Chips.
  4. High Level Synthesis and Design of Microprocessor Architectures.
  5. Design of High Speed Logic Cells and Analog and Mixed A/D Circuits.
  6. Fuzzy Logic and Neural Networks.
  7. Thin Films.
  8. Fibre Pigtailing.
Power Electronics and Control Area
  1. ASIC and Gate Array Implementation of Power Electronics Circuits.
  2. PWM Techniques and Their Applications Including Microprocessors.
  3. Position and Velocity Control Techniques in DC Drives.
  4. Modeling and Analysis of Control of Complex Plants.
  5. Field Bus Concepts of Networking.

Areas of Co-operation for 1996-97

Microelectronics Area
  1. Semiconductor Device Modeling and Reliability.
  2. High Level Synthesis and Design of Microprocessor Architectures.
  3. Cell-Level Designs.
  4. Mixed Signal Designs.
  5. Fuzzy Logic and Neural Networks.
  6. Fibre Pigtailing.
Power Electronics and Related Areas
  1. ASIC and Gate Array Compilation of Power Electronics Circuits.
  2. PWM Techniques and Their Applications Including Microprocessors.
  3. Switched Reluctance Motors and Drives.
  4. Modeling and Analysis of Complex Plants.

APPENDIX II

Co-ordination Committee for 1994-95

  1. Prof. B. C. Nakra (Director, IIT Delhi)
  2. Prof. R. N. Biswas (Director, CEERI)
  3. Prof. D. Nagchoudhuri (Co-ordinator, IIT, Delhi side)
  4. Dr. Chandra Shekhar (Co-ordinator, CEERI side)
  5. Prof. C. M. Bhatia (Department of Electrical Engineering, IIT, Delhi)
  6. Sh. Rahul Verma (Industrial Electronics Group, CEERI)

Co-ordination Committee for 1995-96 and 1996-97

  1. Prof. V. S. Raju (Director, IIT, Delhi)
  2. Prof. R. N. Biswas (Director, CEERI)
  3. Prof. D. Nagchoudhuri (Co-ordinator, IIT, Delhi side)
  4. Dr. Chandra Shekhar (Co-ordinator, CEERI side)
  5. Prof. C. M. Bhatia (Department of Electrical Engineering, IIT, Delhi)
  6. Sh. Rahul Verma (Industrial Electronics Group, CEERI)

APPENDIX III

1994-95

Technical Sub-committee for Microelectronics
IIT, DelhiCEERI, Pilani
1. Prof. D. Nagchoudhuri 1. Dr. Chandra Shekhar
2. Dr. G. S. Visweswaran 2. Sh. D. P. Runthala
3. Dr. Sheel Aditya 3. Dr. P. Suryanarayana

Technical Sub-committee for Control and Power Electronics
IIT, DelhiCEERI, Pilani
1. Prof. C. M. Bhatia 1. Sh. Rahul Verma
2. Dr. S. S. Murthy 2. Sh. V. N. Waliwadekar
3. Prof. Madan Gopal 3. Sh. K. C. S. Murthy

1995-96

Technical Sub-committee for Microelectronics
IIT, DelhiCEERI, Pilani
1. Prof. D. Nagchoudhuri 1. Dr. Chandra Shekhar
2. Dr. G. S. Visweswaran 2. Sh. D. P. Runthala
3. Dr. Sheel Aditya 3. Dr. O. P. Daga

Technical Sub-committee for Control and Power Electronics
IIT, DelhiCEERI, Pilani
1. Prof. C. M. Bhatia 1. Sh. Rahul Verma
2. Dr. S. S. Murthy 2. Sh. K. C. S. Murthy
3. Dr. R. K. P. Bhatt 3. Dr. P. Bhanuprasad

1996-97

Technical Sub-committee for Microelectronics
IIT, DelhiCEERI, Pilani
1. Prof. D. Nagchoudhuri 1. Dr. Chandra Shekhar
2. Dr. G. S. Visweswaran 2. Sh. D. P. Runthala
3. Dr. M. Jagadesh Kumar 3. Dr. V. K. Khanna

Technical Sub-committee for Control and Power Electronics
IIT, DelhiCEERI, Pilani
1. Prof. C. M. Bhatia 1. Sh. Rahul Verma
2. Dr. S. S. Murthy 2. Sh. V. N. Waliwadekar
3. Dr. R. K. P. Bhatt 3. Dr. P. Bhanuprasad

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Updated : August 7, 1997
Created : July 25, 1997


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