MCIT/DIT-SMDP LMDs TOPICS

Various Learning Materials (LMs) developed under DIT's SMDP programme are as follows :

Learning Material Development Distribution
S. No.	Code	LM Topic	Co-ordinating RC
1.	B-1	VLSI Fabrication Technology	IIT-Bombay
2.	B-2	Semiconductor Devices and Modeling	IIT-Kanpur
3.	B-3	Introduction to Digital VLSI Design	IIT-Madras
4.	B-4	VLSI Subsystem Design	IIT-Kharagpur
5.	B-5	Analog IC Design	IIT-Delhi
6.	B-6	Circuit Simulation	IISc-Bangalore
7.	B-7	High-Level VLSI Design	CEERI-Pilani
8.	B-8	Combinatorial Algorithms for VLSI CAD	IIT-Bombay
9.	E-1	Mixed-Signal IC Design	IIT-Madras
10.	E-2	VLSI Systems and Architectures	CEERI-Pilani
11.	E-3	Reconfigurable Computing	IIT-Bombay
12.	E-4	VLSI Testing and Testability	IIT-Kanpur
13.	E-5	System Hardware Design	IIT-Bombay
14.	E-6	Hardware-Software Codesign	IIT-Delhi
15.	E-7	Low-Power Design Techniques	IISc-Bangalore
16.	E-8	VLSI Interconnect Analysis	IIT-Kharagpur
17.	E-10	Advanced System Architectures	IIT-Kharagpur
18.	L-1	Physical Design Lab	IISc-Bangalore
19.	L-2	High-Level Design Lab (VHDL)	IISc-Bangalore
20.	L-3	High-Level Design Lab (Verilog)	CEERI-Pilani
21.	L-4	FPGA Design Lab	IIT-Delhi
22.	L-5	Process Technology Lab	IIT-Kharagpur
23.	L-6	VLSI Subsystem Design Lab	CEERI-Pilani
24.	L-7	Device Modeling Lab	IIT-Bombay
25.	L-8	Analog Design Lab	IIT-Madras

"E-9 : VLSI Design Standards" is to be developed in future.

Contact Raj Singh for any suggestions or problems.

_{Updated : February 16, 2005

Created : September 17, 1999}