VLSI Design Projects of CEERI's IC Design Group

_{Updated : March 28, 2006

Created : July 25, 1997}

Application Specific Processor Based Speech Synthesis Technology Development for Hindi Language (ASPS) sponsored by MCIT/DIT at CEERI, Pilani has been successfully completed.

The duration of the project was over THREE-AND-HALF (3.5) years starting from March, 2001 upto December, 2004.

An Application Specific Instruction-set Processor (ASIP) has been designed, developed and implemented using a prototyping board from M/s Xess on a Xilinx Spartan2e (300,000 gates) FPGA device for the Klatt's parameteric speech synthesis engine -- ``voice chip''.

Special Manpower Development for VLSI Design and Related Software (SMDP) sponsored by MCIT/DIT at CEERI, Pilani was completed in March, 2005.

The project involved 19 institutes in total : 7 RCs and 12 PIs. The duration of the project was for about SIX (6) years starting from December, 1998 upto March, 2005.

The Resource Centers (RCs) were :

The RCs generated Learning Material (LM) that in turn was to be used by the PIs. The list of various LMs to be developed under the project is given here.

The RCs conducted Instruction Enhancement Programme (IEP) covering the various LM topics. The calendar for the IEPs is given here.

The Participating Institutes (PIs) are :

(North) Thapar Institute of Engineering and Technology (TIET), Patiala.
(North) Roorkee University, Roorkee.
(North) BHU-Institute of Technology (BHU-IT), Varanasi.
(East) Bengal Engineering College (BEC), Howrah.
(East) Jadavpur University, Jadavpur.
(East) REC, Rourkela.
(South) REC, Warangal.
(South) PSG College of Engineering, Coimbatore.
(South) KREC, Suratkal.
(West) VRCE, Nagpur.
(West) GSITS, Indore.
(West) Malaviya REC, Jaipur.

The PIs were able to run introductory courses on VLSI Design at the final year B. Tech. / B. E. level (initially) and most of them gradually moved towards running post-graduate courses or degree programmes related to Microelectronics.

All the PIs introduced the basic courses on VLSI Design at B. Tech. / B. E. level.

Another major project completed in the past is Design of a 68010-Compatible Microprocessor for Telecommunication Applications (OTEN).

A Microprocessor, instruction-set compatible with MC 68010, has been designed from scratch (starting from the Programmer's Reference Manual for the MC 68010 processor).

The processor architecture was iteratively optimized so as to execute all the instructions with applicable addressing modes in the same number of clock cycles as the MC 68010 microprocessor.

In order to make the design portable (across foundries), VHDL (RT-Level) and synthesis approach was used.

Entire methodology for design and optimization at RT-level was established.

Methodology for optimization of control-store was established.

Special software was developed to generate functional test vectors for the processor.

The list of various projects handled till date are :

Application Specific Processor Based Speech Synthesis Technology Development for Hindi Language (2001-04).
Special Manpower Development for VLSI Design and Related Software (1998-2005).
20 MHz equivalent of the MC 68010 microprocessor (1993-97).
Controller for multi-channel analog data acquisition (1991-93).
Single-chip controller for microwave ovens (1990-92).
A 3-micron CMOS cell library for academic and R&D community (1990-92).
Serial Data Link Controller (HDLC) chip (1988-91).
16-bit PWM co-processor for variable speed AC drives (1985-87).

Help for various circuits/devices layouts designed by other groups (1984-97).
A CAD tool for making masks from CIF code for CEERI's Electromask facility (1989-95).
A number of CMOS/NMOS process characterisation vehicles (1984-94).

Teaching and projects under the CEERI-BITS MoU continue as usual. See the Group's academic teaching activities for more information.

Contact Raj Singh for any suggestions or problems.